CAN / CAN-FD Bit Timing Calculator
Resolve CAN bit timing (BRP, tq, phase segments, SJW) and sample point from clock and bitrate, plus CAN-FD DLC payload mapping.
Sample input is pre-filled and editable. Everything runs locally in your browser — nothing is uploaded.
| DLC | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DLC → bytes | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 12 | 16 | 20 | 24 | 32 | 48 | 64 |
FAQ
Classic CAN typically 75–87.5% (CiA recommends 87.5%); CAN-FD data phase 70–80%. Longer buses need a later sample point, but keep enough Phase2 for resynchronisation.
This tool requires an integer tq count (8–25 tq per bit). That is a tool limitation, not a universal controller limit — some IPs support wider tq or fractional dividers, and CAN-FD has a separate data-phase timing. Consult the reference manual.
How to use
The article body below is currently available in full only in Chinese; the interface, titles, descriptions and FAQ follow your selected language.
- 填入 MCU 的 CAN 外设时钟（注意是外设时钟，不是系统主频）。
- 选择目标位速率与期望采样点。
- 结果给出 BRP、每比特 tq、SJW/Prop/Phase1/Phase2、实际位速率与实际采样点偏差。其中 Prop 固定为 0，传播段合并进 Phase1，需按收发器延迟自行拆分；SJW 为本工具给出的建议值，不替代网络设计校核。
寄存器写入时：BTR 的 BRP = 结果值 - 1（多数 IP 核），TSEG1 = Prop + Phase1，TSEG2 = Phase2，SJW = 结果值 - 1。不同厂商 IP 的字段偏移略有差异，请对照参考手册。
CAN-FD 载荷长度
经典 CAN 数据长度 0–8 字节直接对应 DLC 0–8。CAN-FD 在 DLC 9–15 使用非连续映射（12/16/20/24/32/48/64），因此不能用 DLC × 8 推算载荷长度——这是移植代码时最常见的坑。
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